A high-speed SAR ADC based on segmented redundant capacitor DAC
Analog-to-digital converter is a significant block in communication system which requires high sampling rate and high resolution.This paper proposed a high-speed successive approximation analog-to-digital converter(SAR ADC)based on segmented redundant capacitor array.By introducing a segmented redundant capacitor array,the design scheme can reduce the area and power consumption,and tackles the insufficient DAC settling on ADC performance under high-speed sampling.Through noise analysis,a two-stage dynamic comparator is designed,and the accuracy of ADC is improved under the premise of high-speed performance.The proposed SAR ADC is designed in SMIC55nm CMOS technology with the supply voltage of 1.2V and sampling frequency of 100MS/s,the pre-simulation result shows that SNDR is 73.27dB and ENOB is up to 11.87bit.
SAR ADCsegment capacitor arrayredundantnoise analysis
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