A hardware acceleration circuit for image resizing
Deep learning algorithm has been widely used in the field of image recognition,deep learning needs to do a lot of data transmission and convolution operations,the speed and data bandwidth requirements are very high.The project background of this paper is to use FPGA scheme to realize face recognition based on MTCNN.Image scaling is a step in MTCNN algorithm.Images are usually cached in DDR,and the processing of image data is limited by the bandwidth of DDR.In this paper,the 16-byte wide data transmission of DDR in this project is taken as an example,and the hardware algorithm of"position lookup and bucket shifter"is used to realize the parallel pipeline-flow operation of data input and output After testing,the speed of this algorithm is about 6 times that of conventional algorithm.
万方数据
维普
