An Output-Capacitorless Low-Dropout Regulator with High Power Supply Rejection
Low Dropout Regulator(LDO)circuits require low input-to-output voltage differences and high supply rejection ratios.In this paper,feed-forward ripple cancellation circuit and negative capacitance circuits are used to realize the enhancement of power supply noise rejection capability of capacitorless LDO with high power supply rejection ratio in the sub-10 KHz band and in the 1 MHz band,respectively,under low input-output voltage differ-ence(≤ 0.2 V)conditions.In addition,the proposed scheme realizes inter-stage power supply noise constraints by adjusting the gain of the second stage error amplifier,which further improves the power supply rejection ratio.In this paper,the proposed LDO circuit is designed and simulated based on SMIC 55 nm process.The results show that the designed LDO achieves a stable 1.6 V output voltage at 1.8 V input voltage,an input-output voltage difference ≤0.2 V,a PSRR greater than 75 dB in all frequency bands up to 1 MHz,and a noise density of 15 µ VRMS in the 10～100 KHz band.In addition,the LDO achieves a linear tuning ratio of 1.43 mV/V,a load tuning ratio of 10 μ V/mA,an overall circuit consumption quiescent current of 76 μ A.
high power supply rejection ratio(PSRR)feed-forward ripple cancellation(FFRC)negative capaci-tance circuit(NCC)capless LDO
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维普
