基于新型环形放大器的低功耗Pipelined SAR ADC
Low power consumption Pipelined SAR ADC based on a novel ring amplifier
李树明1
作者信息
摘要
针对流水线型逐次逼近模数转换器(Pipelined SAR ADC)中残差放大器的核心运放功耗过高,从而严重限制ADC能效上限的问题,本文提出了一种新型的基于CMOS开关的自偏置全差分环形放大器(CMOS Self-biased Fully Differential Ring Amplifier,CSFRA),来替代传统运放.CSFRA 通过引入CMOS开关自偏置和全差分结构,同时在非放大时序中关断电路,降低了残差放大器功耗.基于所提CSFRA,配合可降低开关功耗的检测和跳过切换方案,设计了一款12 Bit 10 MS/s的Pipelined SAR ADC.该电路基于MXIC L18B 180 nm CMOS工艺实现,实验结果表明,在10 MS/s的采样率下,该电路的SFDR和SNDR分别为75.3 dB和61.3 dB,功耗仅为944 μW,其中CSFRA功耗仅为368 μ W.
Abstract
To address the problem that the core op-amp of the residual amplifier in pipelined successive approxima-tion analog-to-digital converters(Pipelined SAR ADCs)consumes too much power,thus severely limiting the upper limit of the ADC's energy-efficiency,this paper proposes a novel CMOS switching self-biased Fully Differential Ring Amplifier(CSFRA),to replace the conventional op-amp.CSFRA reduces the power consumption of the residual amplifier by introducing the CMOS switching self-bias and fully differential structure,and at the same time,shutting down the circuit during the non-amplification time period.Based on the proposed CSFRA,together with a detection and skip switching scheme that reduces the switching power consumption,a 12 Bit 10 MS/s Pipelined SAR ADC has been designed,which is realized based on the MXIC L18B 180 nm CMOS process,and the experimental results show that,at a sampling rate of 10 MS/s,the circuit has an SFDR and SNDR of 75.3 dB and 61.3 dB,with a power con-sumption of 944 μ W,of which the CSFRA power consumption is only 368 μ W.
关键词
Pipelined/SAR/ADC/环形放大器/低功耗Key words
Pipelined SAR ADC/ring amplifier/low power consumption引用本文复制引用
出版年
2024
NETL
NSTL
维普
万方数据