A Design of Fast-locking Digital Delayed Phase-Locked Loop
In high-speed memory,it is necessary to use the phase-locked function to ensure that the output clock and the system input clock are synchronized.The traditional phase-locked loop(PLL)will have problems such as jitter accumulation,while the traditional delay-locked loop(DLL)has a long theoretical locking time due to the delay chain structure.In this paper,a fast-locking DLL is proposed,which uses two latches to form a waveform phase judg-ment machine and form a status word to realize the locking window judgment mechanism.The design uses the clock pulse to realize the left and right bidirectional movement of the delay chain,so as to achieve faster locking.The simu-lation results show that the circuit can complete the phase synchronization of the input clock and the output clock within 15 cycles,with the locking range of 200 MHz～600 MHz and the peak-to-peak jitter is 50ps.
NETL
NSTL
万方数据
维普
