一种高性能CMOS二级运算放大器的设计
Design of a High-Performance CMOS Two-Stage Operational Amplifier
邓鸿添 1蔡佳奎 1徐铫峰 1金豫浙1
作者信息
摘要
基于0.18µm标准CMOS工艺设计了一款高性能的二级运算放大器,输入级采用pmos差分对输入的折叠式共源共栅结构,输出级采用共源级结构,两者级联实现双端输入单端输出;整个电路由带隙基准源提供稳定的偏置.在1.8V工作电压和0.9V共模电压下进行仿真,该运放静态功耗为1.37mW,开环直流增益为117.36dB,相位裕度为77.73°,单位增益带宽100.4MHz(负载电容2pF),压摆率为51.24V/μs,共模抑制比为109.41dB,负电源抑制比为123.58dB,版图面积为180μm×253.5μm.仿真结果表明本文设计的电路结构稳定,性能优越.
Abstract
A high performance two-stage operational amplifier is designed based on 0.18 µ m standard CMOS tech-nology.The input stage adopts pmos differential input Folded-Cascode and the output stage adopts common-source structure,and the two are cascaded to achieve double-terminal input and single-terminal output.The entire circuit is provided with a stable bias by a band-gap reference source.The simulation results show that the static power con-sumption is 1.37mW,the open-loop gain is 117.36dB,the phase margin is 77.73°,the unit gain bandwidth is 100.4MHz(load capacitance is 2pF),the slew rate is 51.24V/µs,and the common-mode rejection ratio is 109.41dB.The negative power rejection ratio is 123.58dB,and the layout area is 180 μ m × 253.5 µ m.The test results show that the circuit structure of the operational amplifier is stable and its performance is superior.
关键词
折叠式共源共栅/带隙基准/高增益/运算放大器Key words
folded-cascode/bandgap/high gain/operational amplifier引用本文复制引用
出版年
2024
NETL
NSTL
万方数据