Real-Time OFDR Processing Technology Based on Low Error Parallel Computing Acceleration
Objective As a type of fiber-optic sensing technology,optical frequency domain reflection(OFDR)technology has received increasing attention in the field of temperature and stress measurement owing to its high spatial resolution and sensitivity.Many scholars have focused on improving the spatial resolution and extending the detection distance of OFDR.However,with improvements in the spatial resolution and detection distance,the data volume and processing difficulty of OFDR have also shown explosive growth.In static testing,it is permissible to handle hysteresis.However,it is difficult to adapt to situations that require high levels of dynamism and repeatability.In response to this issue,Sheng et al.adopted a data caching method;however,this method is only suitable for short-term real-time requirements and cannot perform long-term operations.Therefore,it is extremely important to design a system that satisfies the real-time processing requirements of OFDR.Specialized calculators and programmable logic devices have proven their advantages for data processing in various fields,and in recent years,GPUs have achieved good results in the fields of artificial intelligence and big data owing to their large number of built-in stream processing units and extremely strong computing power.However,GPUs have high power consumption,high heat generation,a low power-to-energy ratio,and poor external scalability,and they often require synchronous use with computers and acquisition boards.The structure of the FPGA is different from that of the GPU.Although an FPGA does not have a large number of stream processors,its programmability is higher.The FPGA integrates dedicated multipliers or digital signal processing(DSP)units internally,which can provide data processing capabilities while offering strong scalability.In this study,we propose a real-time processing system based on low-error parallel computing acceleration to address the difficulties in OFDR data processing.We optimize the system according to its data characteristics and achieve real-time processing of OFDR data.Methods In this study,we classified the data processing of OFDR and divided it into parts that can be directly processed in real time and parts that are difficult to process in real time.The frequency-sweep nonlinear correction algorithm is the main algorithm that can be processed directly in real time.We propose a frequency-sweep nonlinear correction algorithm using a dual-threshold comparator.A dual-gate limited-latch mechanism was used to reduce the false triggering of false resampling and minimize errors.The parts that are difficult to process in real-time primarily include the spectrum.We used a dual-address loop method in the DDR3 storage chip to achieve FIFO ping pong operation.We designed a kernel based on single-point computing and utilized the parallel scalability of an FPGA to expand multiple computing kernels.Because the DSP48E1 unit in the FPGA can only be used for fixed-point calculations,we analyzed the calculation error and designed a rotation factor with dynamic accuracy that can achieve minimum calculation error while ensuring no overflow in the calculation.Results and Discussions To verify the effectiveness of the algorithm,we built an experimental platform and separately tested the calculation error and time.In the calculation error testing,computers and an FPGA were used to test and analyze the experimental optical path,and all data and local detail data were compared.For comparison,the effective proportion of the input signal is approximately 0.1,the number of calculation points is approximately 110000,and the dynamic bit width of the rotation factor is 23 bit.The maximum calculation error measured is 5.2×10-8,which is less than 10-7,proving that the FPGA is consistent with the computer calculation results.When using a fixed bit width and retesting the same data,the maximum calculation error measured was 6.4×10-6.Therefore,under these testing conditions,the proposed dynamic bit width algorithm can reduce the calculation error by approximately 100 times,and the calculation time was measured multiple times at 500 and 3000 points.The operating times of the FPGA and computer were measured using the oscilloscope and software timer methods,respectively.The results indicate that the FPGA can achieve computational acceleration at various effective points.In the case of 500 points,it can provide 11 times processing speed of the compupter.At 3000 points,it can provide 16 times processing speed of the compupter.Conclusions Through experimental verification,the proposed system can effectively accelerate the process of OFDR data processing and achieve low error.Compared with traditional fixed accuracy,the proposed system reduces the calculation error by approximately two orders of magnitude.Compared with computer processing,the proposed system can obtain faster speed and achieve real-time processing of 20 frame/s.However,this system has several limitations.Real-time data processing cannot be guaranteed when the number of effective OFDR points increases.However,this problem can be solved by upgrading the FPGA chip and using devices with more resources and higher clock frequencies.
optical communicationsoptical frequency domain reflectometerfield programmable gate arrayreal-time processing and demodulationcalculation errorparallel computing
万方数据
维普
