Design of Error-tolerant Booth Multipliers for Computing
Error tolerant computing is an attractive design methodology to achieve low power,high performance and low delay by relaxing the requirement of accuracy.In this paper,error tolerant Booth multipliers are designed based on radix-4 modified Booth encoding algorithms.The error characteristics are also analyzed with respect to the so-called approximation factor that is related to the inexact bit width of the Booth multipliers.Simulation results at 45 nm feature size in CMOS for power,area and delay consumption are also provided;they confirm that the proposed designs significantly improve over existing error tolerant and exact designs with respect to these figures of merit while incurring very modest errors.Case studies for image processing show the validity of the proposed error tolerant Booth multipliers.
booth encoderradix-multipliererror tolerant designlow power
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