A redundancy-aware energy-efficient graph accelerator
Graph plays an essential role in a wide range of real-world applications.Due to graph irregularity,general-purpose processors are not an ideal platform for graph processing.Therefore,there has been a significant interest in developing domain-specific accelerators for graph processing in the past few years.With dedicated hardware specialization,graph accelerators can deliver considerable performance speedups compared to CPUs and GPUs.However,existing graph accelerators perform unnecessary accesses on high-degree vertices when running BFS on power-law graphs,resulting in severe off-chip memory overheads.To solve the problem,we architect JiFeng,a redundancy-aware graph accelerator.When a high-degree vertex finishes execution,JiFeng aggressively skips all its edges to avoid redundant memory accesses.Several software/hard ware co-designs are proposed to improve memory efficiency and load-balance.We have implemented JiFeng in RTL and evaluated it on a Xilinx Alveo U55C accelerator card.JiFeng achieves at most 461.2 GTEPS throughput and 12.5 GTEPS/W energy efficiency,and ranks 2nd in the SMALL DATA list of GreenGraph500.
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