VLSI architecture for multi bit plane cyclic embedded block coding with optimized truncation encoding
Objective JPEG2000 is composed of multiple image encoding algorithms,with embedded block coding with optimized truncation(EBCOT)serving as the core encoding algorithm.EBCOT is a key algorithm in JPEG2000 image com-pression standard,and its coding results directly affect the compression quality of images.EBCOT encoding is internally composed of Tier1 encoding and Tier2 encoding.Tier1 encoding is responsible for encoding the quantized wavelet coeffi-cients.This process is the core of EBCOT encoding to achieve compression effect;thus,it requires substantial resources in hardware implementation to ensure the efficiency and accuracy of data output.Tier2 encoding is responsible for truncating and packaging the encoding results of Tier1,and its encoding results affect the compression rate and compression effect of JPEG2000.Tier2 encoding takes less time,and the rate distortion calculation can be completed simultaneously with Tier1 encoding,shortening the compression time.At the same time,given the inherent intricacies of the algorithm,a diligent consideration of hardware resource utilization is imperative during its implementation in hardware.This cautious approach ensures the judicious employment of limited hardware resources toward the realization of an efficient EBCOT encoding tai-lored for JPEG2000 image compression.Therefore,to solve these problems,a parallel EBCOT coding very large scale inte-gration circuit(VLSI)architecture with all pass multi bit plane cyclic coding is proposed.Method The EBCOT encoding process has two main parts:Tier1 encoding and Tier2 encoding.A novel encoding window structure,i.e.,multi bit plane cyclic encoding(MBCE),is designed to address the encoding speed in the Tier1 encoding part.The encoding window con-sists of four encoding columns:completed encoding column,current encoding column,prediction column,and updated prediction column.The 5x4 encoding window in question exploits the encoding information of each bit plane layer to par-allelize the encoding process,effectively breaking the interplane correlation and remarkably improving the encoding effi-ciency.Additionally,compared with traditional parallel encoding structures,this encoding window utilizes few encoding resources by reusing encoders.Furthermore,it supports encoding arbitrary-sized code blocks.With regard to the pass dis-tortion calculation in the Tier2 encoding part,a pipeline calculation structure is designed to run in parallel with Tier1 encoding.By fetching the bit plane coding results in Tier1 encoding,the complex multiplication and addition operations are split into multiple stages of pipeline,enabling the structure to work at a higher frequency on FPGA and improving the overall encoding efficiency.Moreover,this structure can run in parallel with Tier1 encoding without compromising the throughput of Tier1 encoding.By designing an efficient Tier1 encoding structure and a multistage parallel encoding struc-ture for Tier2,the parallel structure between them reduces the time required for EBCOT encoding and improves the overall encoding efficiency while ensuring the image compression quality.By optimizing the Tier1 and Tier2 encoding processes and utilizing parallel processing techniques,the proposed MBCE architecture aims to improve the efficiency of EBCOT encoding,reduce the encoding time,and enhance the overall image compression quality.Result The MBCE encoding structure proposed in Verilog is described at RTL level,and FPGA is selected as the experimental verification platform for this structure.The structural encoding rate,encoding compression effect,and the required resources of the encoding struc-ture are compared with the existing EBCOT optimized structure.In terms of encoding efficiency,the proposed structure shows remarkable improvement compared with the bit plane parallel encoding structure.Moreover,the proposed MBCE structure considerably reduces the required encoding cycles in image compression compared with several existing EBCOT encoding VLSI structures.By implementing whole pass parallelism,the encoding efficiency is enhanced.Additionally,the hardware resource utilization and maximum operating frequency of the proposed structure are superior to several EBCOT structures mentioned in the literature.In the 1:8 lossless compression mode of the three-level 5/3 wavelet transform with a block size of 32 x 32,the MBCE structure is used to compress the same 512 × 512 pixels 8-bit standard grayscale image.Compared with the JPEG2000 standard image compression software Jasper,Openjpeg,and Kakadu,the peak signal-to-noise ratio error is less than 0.05 dB.On the xc4vlx25 model FPGA,its operating frequency can reach 193.1 MHz,and it can process 370 frames per second.Conclusion The proposed MBCE structure in this study not only exhibits low resource utilization and high encoding throughput but also ensures short encoding cycles.The JPEG2000 compression system using the EBCOT structure proposed in this study has been tested and found to achieve a maximum image quality deviation com-pared with images encoded using standard JPEG2000 compression software.This remarkable deviation demonstrates the effectiveness of the proposed MBCE structure in preserving image quality during the compression process.The compressed images maintain a high level of fidelity comparable with those produced by established JPEG2000 compression software.This improvement in image quality is attributed to the optimized Tier1 and Tier2 encoding processes and the utilization of parallel processing techniques in the MBCE architecture.The resulting enhancement in image compression quality high-lights the potential of the proposed MBCE structure for improving JPEG2000-based image compression.
万方数据
维普
