首页|Improving the electrical performances of InSe transistors by interface engineering
Improving the electrical performances of InSe transistors by interface engineering
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InSe has emerged as a promising candidate for next-generation electronics due to its predicted ultrahigh electrical per-formance.However,the efficacy of the InSe transistor in meeting application requirements is hindered due to its sensitivity to interfaces.In this study,we have achieved notable enhancement in the electrical performance of InSe transistors through interface engineering.We engineered an InSe/h-BN heterostructure,effectively suppressing dielectric layer-induced scat-tering.Additionally,we successfully established excellent metal-semiconductor contacts using graphene ribbons as a buffer layer.Through a methodical approach to interface engineering,our graphene/InSe/h-BN transistor demonstrates impres-sive on-state current,field-effect mobility,and on/off ratio at room temperature,reaching values as high as 1.1 mA/μm,904 cm2·V-1·s-1,and>106,respectively.Theoretical computations corroborate that the graphene/InSe heterostructure shows significant interlayer charge transfer and weak interlayer interaction,contributing to the enhanced performance of InSe transistors.This research offers a comprehensive strategy to elevate the electrical performance of InSe transistors,paving the way for their utilization in future electronic applications.
two-dimensional materialsInSevan der Waals heterostructureelectrical performancescharge density difference
曹天俊、郝松、吴晨晨、潘晨、戴玉頔、程斌、梁世军、缪峰
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Institute of Brain-Inspired Intelligence,National Laboratory of Solid State Microstructures,School of Physics,Collaborative Innovation Center of Advanced Microstructures,Nanjing University,Nanjing 210093,China
Institute of Interdisciplinary Physical Sciences,School of Physics,Nanjing University of Science and Technology,Nanjing 210014,China
National Natural Science Foundation of China国家自然科学基金国家自然科学基金国家自然科学基金国家自然科学基金国家自然科学基金中国科学院战略规划重点项目