首页|PPAA: a parallel primitive assembly accelerator in graphics processor

PPAA: a parallel primitive assembly accelerator in graphics processor

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Primitive assembly is an inevitable procedure of graphics rendering which performs the objects preparation for the following steps,however,the conventional approaches suffer from some issues,such as the missing of surface attribute,mismatch of color mode for clipped primitives,and performance bottleneck of rendering pipeline.This paper takes all these issues into considerations,and proposes a parallel primitive assembly accelerator (PPAA) which can solve not only the functional problems but also improve the shading performance.The register transfer level (RTL) circuit is designed and the detailed approach is presented.The prototype systems are implemented on Xilinx field programmable gate array (FPGA) XC6VLX550T and Altera FPGA EP2C70F896C6.The experimental results show that PPAA can accomplish the assembly tasks correctly and with higher performance of 1.5x and 2.5x of two previous implementations.For the most frequently independent primitives,the PPAA can efficiently enhance the throughput by squeezing out the pipeline bubbles and by balancing the pipeline stages.

primitive assemblyparallel acceleratorprimitive characteristicsgraphics processor

Deng Junyong、Xie Xiaoyan、Liu Yang、Tian Pu

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School of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an 710121, China

School of Computer, Xi'an University of Posts and Telecommunications, Xi'an 710121, China

This work was supported by National Natural Science Foundation of ChinaThis work was supported by National Natural Science Foundation of ChinaThis work was supported by National Natural Science Foundation of ChinaThis work was supported by National Natural Science Foundation of ChinaThis work was supported by National Natural Science Foundation of ChinaShaanxi International Science and Technology Cooperation ProgramShaanxi Province Co-ordination Innovation Project of Science and TechnologyShaanxi Provincial Key R&D Plan

61834005617724176160237761802304618740872018KW-0062016KTZDGY02-04-022017GY-060.

2020

中国邮电高校学报(英文版)
北京邮电大学

中国邮电高校学报(英文版)

CSCDEI
影响因子:0.419
ISSN:1005-8885
年,卷(期):2020.27(2)
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