首页|Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

Energy-efficient reconfigurable processor for QC-LDPC via adaptive coding-voltage-frequency tuning

扫码查看
原文链接
  • NETL
  • NSTL
  • 万方数据
To apply a quasi-cyclic low density parity check(QC-LDPC)to different scenarios,a data-stream driven pipelined macro instruction set and a reconfigurable processor architecture are proposed for the typical QC-LDPC algorithm.The data-level parallelism is improved by instructions to dynamically configure the multi-core computing units.Simultaneously,an intelligent adjustment strategy based on a programmable wake-up controller(WuC)is designed so that the computing mode,operating voltage,and frequency of the QC-LDPC algorithm can be adjusted.This adjustment can improve the computing efficiency of the processor.The QC-LDPC processors are verified on the Xilinx ZCU102 field programmable gate array(FPGA)board and the computing efficiency is measured.The experimental results indicate that the QC-LDPC processor can support two encoding lengths of three typical QC-LDPC algorithms and 20 adaptive operating modes of operating voltage and frequency.The maximum efficiency can reach up to 12.18 Gbit/(s·W),which is more flexible than existing state-of-the-art processors for QC-LDPC.

quasi-cyclic low density parity check(QC-LDPC)dynamic voltage and frequency scaling(DVFS)reconfigurable computingcoarse-grained reconfigurable arrays(CGRAs)

Chang Libo、Hu Yiqing、Du Huimin、Wang Jihe

展开 >

School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China

School of Computer Science,Northwestern Polytechnical University,Xi'an 710072,China

国家重点研发计划Key Scientific Research Program of Shaanxi Provincial Department of EducationChina Civil Aviation Airworthiness Center Open Foundation

2019YFB180360022JY059SH2021111903

2024

10.19682/j.cnki.1005-8885.2024.0005

中国邮电高校学报(英文版)
北京邮电大学

中国邮电高校学报(英文版)

影响因子：0.419
ISSN：1005-8885
年,卷(期)：2024.31(2)
  • 22