首页|Design and implementation of a multi-tile parallel scanning rasterization accelerator
Design and implementation of a multi-tile parallel scanning rasterization accelerator
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In the design of a graphic processing unit(GPU),the processing speed of triangle rasterization is an important factor that determines the performance of the GPU.An architecture of a multi-tile parallel-scan rasterization accelerator was proposed in this paper.The accelerator uses a bounding box algorithm to improve scanning efficiency.It rasterizes multiple tiles in parallel and scans multiple lines at the same time within each tile.This highly parallel approach drastically improves the performance of rasterization.Using the 65 nm process standard cell library of Semiconductor Manufacturing International Corporation(SMIC),the accelerator can be synthesized to a maximum clock frequency of 220 MHz.An implementation on the Genesys2 field programmable gate array(FPGA)board fully verifies the functionality of the accelerator.The implementation shows a significant improvement in rendering speed and efficiency and proves its suitability for high-performance rasterization.
NETL
NSTL
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