A low-jitter high-speed charge-pump phase-locked loop (CPPLL) suitable for high-speed SerDes serial link was designed using 65 nm CMOS technology. Loop bandwidth and circuit structure of voltage-controlled oscillator (VCO),charge pump (CP),phase frequency detector (PFD) were optimized to reduce jitter caused by voltage ripple and internal noise. CPPLL can achieve a stable clock signal with the smaller jitter offset while meeting the wide frequency range and high speed requirements of SerDes link. Chip area including the entire pads is 0.309 mm2. The measurement results show that CPPLL can generate a 10.9-12 GHz clock signal and exhibit a phase noise of −111.47 dBc/Hz and a reference spur of −25.14 dBc and a figure-of-merit (FoM) of −223.5 dB at 10 MHz offset. It takes 600 μs to generate a stable 11.3 GHz clock signal,and its RMS jitter is 973.9 fs when the reference frequency is 706.25 MHz,which is approximately 0.065 UI. The power consumption is 47.3 mW at the supply voltage of 1.2 V. The proposed phase-locked loop (PLL) is suitable for high-speed communication link systems at 20 Gb/s and above.
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