PCIE Power Estimation Flow Optimization based on Hardware Accelerator
Highly accurate power estimation was crucial for PPA(Performance-Power-Aera)design.A"tentative test+referenced test+exhaustive test"three-step power estimation flow was proposed in this paper.The peak toggle threshold value could be obtained with the help of an online toggle processing unit in the tentative test step.And the correspondence of power to toggle could be obtained in the referenced test.At last the peak power could be calculated in the exhaustive test step.It could o-vercome,by utilizing the geometric proportion between dynamic power and toggle,the shortcoming of normal power estimation flow when adapted to design with dynamic IO device such as PCIE.Fine-grained DUT partition strategy was proposed and adopted in this paper to promote peak power cases and flatten the gap of the test bench scale between emulation and Si-chip.A method a-bout promoting peak power was also provided based on comparison datum.The strategies proposed in this paper were applied to the power estimation of domestic PCIE modules of high performance artificial intelligence CPU SUPER-1 with the accuracy of more than 90％.
NETL
NSTL
万方数据
