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Design of 512-bit logic process-based single poly EEPROM IP

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A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process.The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2,about 37％ smaller than the conventional cell.Also,a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip.To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices,an EEPROM core circuit and a DC-DC converter were proposed.Simulation results for the designed EEPROM IP based on the 0.18 μm logic process show that the power consumptions in read mode,program mode and erase mode are 11.82,25.15,and 24.08 μW,respectively,and the EEPROM size is 0.12 mm2.

single poly EEPROM cellFowler-Nordheim tunnelinglogic processradio frequency identificationsmall area

JIN Li-yan、JANG Ji-Hye、YU Yi-ning、HA Pan-Bong、KIM Young-Hee

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Department of Electronic Engineering, Changwon National University, Changwon 641-773, Korea

supported by the Industrial Strategic Technology Development Program Funded by the Ministry of Knowledge Economy,Korea

10039239

2011

10.1007/sl1771-011-0939-4

中南大学学报(英文版)
中南大学

中南大学学报(英文版)

SCIEI
影响因子：0.47
ISSN：2095-2899
年,卷(期)：2011.18(6)
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