In order to explore the layout method used to minimize parasitic inductance in a half bridge circuit formed by combining discrete devices and PCBs,an optimized layout method for discrete devices on PCB based on the concept of parasitic inductance in the commutation circuit is proposed.Subsequently,finite element simulation software is used to evaluate and verify the parasitic inductance generated by different layout methods,and combined with LTspice circuit simulation software to evaluate the differences in voltage stress and switching losses of switching devices caused by different layout methods.Finally,the superiority of the optimized layout half bridge circuit designed was verified through double pulse experiments.The design method of the half bridge circuit provided provides theoretical and technical support for the layout of discrete devices on PCBs.
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