Design of Parallel Multiplier Based on Radix-4 Booth Coding
Speed and area are two basic indexes to evaluate the performance of multiplier unit. Aiming at the prob-lem of balancing layout area and transmission delay in current multiplier design,a new 16-bit signed fixed-point multiplier was designed by using Radix-4 Booth algorithm. In the process of partial product generation,firstly,the complementary code circuit for multiplier was improved,and then the modified Booth encoder and decoder with Ra-dix-4 were optimized. The structure used less logic gate resources and was easy to parallelize the input bits. In the Wallace compression circuit,the symbol extension bits were preprocessed and a new compressor structure was de-signed to optimize the whole Wallace compression module. In the second stage of compression,the ripple carry ad-der structure was used to calculate the high bits in advance,which reduced the sum bits of multi-bit pseudo-sums. In the summation circuit,a two-stage carry look-ahead adder structure was used to shorten the transmission delay of the critical path and avoid increasing the chip area,thus improved the running speed of the multiplier. Compared with the existing multiplier structure,the new fixed-point multiplier reduced the area by 12.0％ and the delay by 20.5％.
万方数据
维普
