首页|Patent Issued for Synchronisation for a multi-tile processing unit (USPTO 119285 23)
Patent Issued for Synchronisation for a multi-tile processing unit (USPTO 119285 23)
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By a News Reporter-Staff News Editor at Robotics & Machine Learning Daily News Daily News-Graphcore Limited (Bristol, United Kin gdom) has been issued patent number 11928523, according to news reporting origin ating out of Alexandria, Virginia, by NewsRx editors. The patent's inventors are Alexander, Alan (Wotton-under-Edge, GB), Felix, Steph en (Bristol, GB), Huse, Lars Paul (Oppegaard, GB), Knowles, Simon (Corston, GB), Lacey, David (Cheltenham, GB), Osborne, Richard (Bristol, GB), Wilkinson, Danie l John Pelham (Bristol, GB). This patent was filed on September 1, 2021 and was published online on March 12, 2024. From the background information supplied by the inventors, news correspondents o btained the following quote: "In the context of processing data for complex or h igh volume applications, a processing unit for performing the processing of that data may be provided. The processing unit may function as a work accelerator to which processing of certain data is offloaded from a host system. Such a proces sing unit may have specialised hardware for performing specific types of process ing. "As an example, one area of computing in which such a specialised accelerator su bsystem may be of use is found in machine intelligence. As will be familiar to t hose skilled in the art of machine intelligence, a machine intelligence algorith m is based around performing iterative updates to a "knowledge model", which can be represented by a graph of multiple interconnected nodes. The implementation of each node involves the processing of data, and the interconnections of the gr aph correspond to data to be exchanged between the nodes. Typically, at least so me of the processing of each node can be carried out independently of some or al l others of the nodes in the graph, and therefore large graphs expose great oppo rtunities for multi-threading. Therefore, a processing unit specialised for mach ine intelligence applications may comprise a large degree of multi-threading. On e form of parallelism can be achieved by means of an arrangement of multiple til es on the same chip (i.e. same die), each tile comprising its own separate respe ctive execution unit and memory (including program memory and data memory). Thus separate portions of program code can be run in parallel on different ones of t he tiles.
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