首页|Patent Issued for Tracing synchronization activity of a processing unit (USPTO 1 1907772)
Patent Issued for Tracing synchronization activity of a processing unit (USPTO 1 1907772)
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Reporters obtained the following quote from the background information supplied by the inventors: “A processing unit may be provided as part of a device, e.g. a n integrated circuit, and used for performing operations on data. In context of processing data for complex or high volume applications, such a processing devic e may be a subsystem to which processing of certain data is offloaded from a hos t system. Such a work accelerator may have a specialised hardware for performing specific types of processing. “As an example, one area of computing in which such a specialised accelerator su bsystem may be of use is found in machine intelligence. As will be familiar to t hose skilled in the art of machine intelligence, a machine intelligence algorith m is based around performing iterative updates to a “knowledge model”, which can be represented by a graph of multiple interconnected nodes. The implementation of each node involves the processing of data, and the interconnections of the gr aph correspond to data to be exchanged between the nodes. Typically, at least so me of the processing of each node can be carried out independently of some or al l others of the nodes in the graph, and therefore large graphs expose great oppo rtunities for multi-threading. Therefore, a work accelerator specialised for mac hine intelligence applications may comprise a large degree of multi-threading. O ne form of parallelism can be achieved by means of a processor comprising an arr angement of multiple tiles on the same chip (i.e. same die), each tile comprisin g its own separate respective processing unit and memory (including program memo ry and data memory). Thus separate portions of program code can be run in parall el on different ones of the tiles. The tiles are connected together via an on-ch ip interconnect which enables data to be exchanged between them. Such an acceler ator may function as a subsystem for a host system to perform parallel processin g of data sets provided to it.
BusinessEmerging TechnologiesGraphco re LimitedMachine IntelligenceMachine Learning
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