首页|Patent Issued for Method and apparatus for debonding temporarily bonded wafers in wafer-level packaging applications (USPTO 11996384)
Patent Issued for Method and apparatus for debonding temporarily bonded wafers in wafer-level packaging applications (USPTO 11996384)
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Reporters obtained the following quote from the background information supplied by the inventors: “Three-dimensional (3D) chip technologies have been gaining po pularity in the microelectronics industry because of their advantages such as sh orter circuit paths, higher performance, less power consumption and faster heat dissipation. With 3D chip technologies, multiple heterogeneous silicon wafers can be stacked vertically to form a 3D integrated circuit. The silicon wafers are relatively thin (50-100 mm) such that they can be interconnected by utilizing through-silicon vias (TSVs).
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