DESIGN AND ANALYSIS OF AN m + n/k MULTIPLIER BASED ON MULTI-PHASE CLOCK

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外文摘要：ABSTRACT. Multiple clock sources are needed in mobile communication devices to drive each system. As a clock source, the authors have previously proposed a frequency multiplier using a double-edge counter and demonstrated its effectiveness. This paper proposes an m + n/k multiplier based on a multi-phase clock. This circuit can realize m + n/k multiplication at non-integer frequencies of the input signal by employing the 1 + n/k divider, proposed by the authors, as the basis for the multi-phase clock counting circuit. The characteristics were verified through simulations using Verilog-HDL. It was clarified that the steady-state frequency error of the output signal relative to the input signal frequency corresponds to a one-phase difference of the multi-phase clock. Furthermore, it was confirmed that a regular multiplied signal is obtained within two cycles of the input signal.

外文关键词：

Frequency multiplierMulti-phase clockSteady-state frequency errorFrequency dividerm + n/k

作者：

DAISHI NISHIGUCHI、MITSUTOSHI YAHARA、YUJIRO HARADA、MASAAKI FUKUHARA、KUNIAKI FUJIMOTO

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作者单位：

Research Institute of Science and Technology

Department of Community and Social Studies

Department of Electrical and Electronic Engineering National Institute of Technology, Kurume College 1-1-1 Komorino, Kurume-shi, Fukuoka 830-8555, Japan

Department of Information and Telecommunication Engineering Tokai University 2-3-23 Takanawa, Minato-ku, Tokyo 108-8612, Japan

Department of Human Information Engineering Tokai University 9-1-1 Toroku, Higashi-ku, Kumamoto-shi, Kumamoto 862-8652, Japan

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出版年：

2025

DOI：

10.24507/ijicic.21.02.423

International journal of innovative computing, information and control

ISSN：1349-4198

年,卷(期)：2025.21(2)