首页|Patent Application Titled 'Three-Dimensional Vertical Interconnect Architecture and Methods For Forming' Published Online (USPTO 20240387458)
Patent Application Titled 'Three-Dimensional Vertical Interconnect Architecture and Methods For Forming' Published Online (USPTO 20240387458)
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Reporters obtained the following quote from the background information supplied by the inventors:“Advances in artificial intelligence have put ever increasing pressure on logic and memory circuits to keepup with the computational requirem ents. As chip processing speeds increase, the amount of time requiredto store a nd retrieve information from memory becomes a bottleneck in machine learning sys tems. Theinventors have observed that the parallel arrangement of logic and mem ory devices has a profound impacton the storage and retrieval time for memory d ata.
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