首页|Efficient VLSI Architectures of Convolution based DWT using Bit Accumulation
Efficient VLSI Architectures of Convolution based DWT using Bit Accumulation
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NETL
NSTL
Springer Nature
The real-time engineering applications concerning audio and image compressions necessitate high-performance VLSI architectures of discrete wavelet transform (DWT). This paper suggests efficient folded VLSI architectures of convolution based 1D/2D-DWT utilizing bit accumulation. In the proposed folded convolution based fixed point 1 D/2D-DWTs, quarter precision Wallace tree multiplier and multiply accumulate circuit (MAC) are incorporated, which accumulate the resultant values in every level of decomposition of the DWT. Here, the n × n-bit quarter precision multiplier and MAC are utilized to execute an n x n-bit or two numbers of n × n/2-bit or four numbers of n/2 × n/2-bit multiplications and MAC operations concurrently, respectively. To enhance the value of peak signal to noise ratio (PSNR) in audio and image compressions, the rounding off operation is performed only at the final level of DWT instead of at each level. Cadence is used to implement all current and proposed DWT designs with 45 nm CMOS technology.
Convolution based DWTDigital Signal ProcessingFIR filterImage CompressionLifting based DWT
Mohamed Asan Basiri M
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Department of Electronics and Communication Engineering, Indian Institute of Information Technology Design and Manufacturing, Kurnool, Andhra Pradesh 518007, India
NETL
NSTL
Springer Nature
