首页|Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit
Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit
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NETL
NSTL
IEEE
Delay lines often face challenges due to input-output nonlinearity and excessive voltage-to-time gain, leading to inaccurate voltage indications and a limited input voltage range. This article presents a complementary voltage-to-time converter (VTC) with an optimized voltage scaling circuit to address these issues. The complementary VTC utilizes both input-voltage-sourced and input-voltage-referenced delay lines. Although each delay line has inherent nonlinearities, the opposite signs of their respective voltage-to-time gains effectively reduce the overall nonlinearity. To further enhance performance, an optimized voltage scaling circuit is incorporated, refining nonlinearity and expanding the input voltage range. Experimental results using UMC 0.18- $\mu $ m technology demonstrate that the proposed circuit achieves excellent linearity, an extended nearly rail-to-rail input voltage range, and robustness against process variations. The VTC achieves a voltage-to-time gain of 13.27 ps/mV, signal to noise and distortion ratio (SNDR) of 32.4 dB, and maintains stable dynamic performance across the working frequency band.
Delay linesDelaysVoltageLinearityElectromagnetic interferenceTransistorsIntegrated circuit modelingGainVery large scale integrationRobustness
NETL
NSTL
IEEE
