A 10-b (9.1-b ENOB), TP-Robust Open-Loop VCO-based ADC in 65 nm CMOS
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NSTL
Elsevier
This brief proposes a 10-bit (9.1-bit ENOB) voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) that operates at 50 MHz sampling frequency and uses pseudo-differential ring VCO (RVCO) with eight stages in 65 nm CMOS technology. The main challenges are the nonlinearity and variations in the voltagefrequency characteristic of the RVCO, which severely diminishes the static and dynamic specifications of the ADC. In this system, a look-up table (LUT) is utilized to overcome the nonlinearity issue by applying the reverse transfer function of the RVCO's voltage-frequency characteristic. Most importantly, a temperature sensor and an equation storage block are employed to solve the problem of the variations derived from temperature and process changes. As a result, the output codes of the ADC are devoid of distortion and quantization noise created due to temperature and process variation. Simulation results show that SNDR improves almost to 55 dB, and the system's associated ENOB is about 9.1. Moreover, the proposed ADC occupies an area of 216 ism x 161 ism, without the LUT and the equation storage block.
Analog-to-digital converter (ADC)Temperature and process compensationQuantization noise-shapingRing voltage-controlled oscillatorDigital calibrationLinearizationVCO-based ADCLUT
NSTL
Elsevier
