Journal of Alloys and Compounds2022,Vol.89812.DOI:10.1016/j.jallcom.2021.162918

(162918)Effects of interfacial oxide layer formed by annealing process on WORM characteristics of Ag/Cu_xO/SiO_x/n~+-Si devices

Chih-Chieh Hsu Sheng-Yen Hua Xuan-Zhi Zhang
Journal of Alloys and Compounds2022,Vol.89812.DOI:10.1016/j.jallcom.2021.162918

(162918)Effects of interfacial oxide layer formed by annealing process on WORM characteristics of Ag/Cu_xO/SiO_x/n~+-Si devices

Chih-Chieh Hsu 1Sheng-Yen Hua 2Xuan-Zhi Zhang3
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作者信息

  • 1. Graduate School of Engineering Science and Technology, National Yunlin University of Science and Technology, 123 University Road, Section 3, Douliu, Yunlin 64002, Taiwan, ROC
  • 2. Department of Electronic Engineering, National Yunlin University of Science and Technology, 123 University Road, Section 3, Douliu, Yunlin 64002, Taiwan, ROC
  • 3. Graduate School of Electronic Engineering, National Yunlin University of Science and Technology, 123 University Road, Section 3, Douliu, Yunlin 64002, Taiwan, ROC
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Abstract

In this paper, we investigate the effects of a SiO_x interfacial layer on ON/OFF current ratios, endurance characteristics and read-disturb immunities of Ag/Cu_xO/SiO_x/n~+-Si write-once-read-many-times (WORM) memories. The Cu_xO active layers were prepared using a sol-gel process. After coating Cu_xO films on n~+-Si substrates, the Cu_xO/n~+-Si samples were annealed in air at 400 °C and 600 °C, respectively, to obtain a SiO_x interfacial layer at the Cu_xO/n + -Si interfaces. The 400 °C-annealed Cu_xO device shows an ON/OFF current ratio of 104. However, degradation of OFF state current (IOFF) with increasing read-pulse cycles and stress time is observed. For the 600 °C-annealed Cu_xO device, stable ON and OFF state currents can be observed both in an endurance test for over 1.2 × 104 read cycles and in a read-disturb test for 2 × 104 s. Moreover, a higher ON/OFF current ratio of 107 is obtained. A rigorous retention test executed at an elevated temperature of 85 °C indicates that the data retention time is expected to last for 10 years. The performance improvement of the 600 °C-annealed Cu_xO device is due to an increase in the thickness of the SiO_x interfacial oxide layer. The mechanism for the influence of the interfacial layer on memory performance is investigated and illustrated. The OFF state current of the memory is limited by hopping and trap-assisted tunneling transport in the SiO_x interfacial layer. In the ON state, conductive paths in the device cause that the carriers can easily migrate by Ohmic and space charge limited conduction.

Key words

Copper oxide/Silicon oxide/Resistive switching/Annealing/Interfacial layer

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出版年

2022
Journal of Alloys and Compounds

Journal of Alloys and Compounds

EISCI
ISSN:0925-8388
被引量2
参考文献量74
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