首页|Towards an FPGA implementation and performance evaluation of a digital carrier synchronizer with a portable emulation environment
Towards an FPGA implementation and performance evaluation of a digital carrier synchronizer with a portable emulation environment
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The work addresses the implementation and performance analysis of a Digital Carrier Synchronizer (DCS), which is a Phase-Locked Loop (PLL), realized using digital circuits. The DCS function is heavily dependent on the Numerically Controlled Oscillator (NCO) and the Loop Filter (LF). The paper examines the performance of two different NCOs and LFs realization in DCS for modern application. The methods presented are Look Up Table (LUT) and Xilinx ROM based NCO for 1st order and 2nd order based LF. We also developed a mathematical model of DCS and analyzed the performance based on stability, locking-time and tracking range. We propose a synthesizable and portable FPGA emulation environment of a DCS. Moreover, we have developed the DCS architecture with respect to a frequency based mathematical model. Finally, our emulation technique is not only involved with the DCS but also can be customized for any data synchronization system that respects the mathematical model.
Digital carrier synchronizerFPGA emulation environmentNumerically controlled oscillatorLoop filterAnalog to digital converterPhase locked loop
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