首页期刊导航|IEEE transactions on circuits and systems, Part II. Express briefs
期刊信息/Journal information
IEEE transactions on circuits and systems, Part II. Express briefs
Institute of Electrical and Electronics Engineers
IEEE transactions on circuits and systems, Part II. Express briefs

Institute of Electrical and Electronics Engineers

月刊

1549-7747

IEEE transactions on circuits and systems, Part II. Express briefs/Journal IEEE transactions on circuits and systems, Part II. Express briefs
正式出版
收录年代

    IEEE Transactions on Circuits and Systems--II: Express Briefs Publication Information

    C2-C2页
      原文链接:
    • NETL
    • NSTL

    IEEE Circuits and Systems Society Information

    C3-C3页
      原文链接:
    • NETL
    • NSTL

    Table of Contents

    C1-C4页
      原文链接:
    • NETL
    • NSTL

    A 43.4-dB Gain 7.6-mW 197.5% Bandwidth Double Noise-Canceling Cryogenic LNA Using Gain Peaking Technique for Multiple Spin Qubit Readout

    Mahesh Kumar ChaubeyYin-Cheng ChangPo-Chang WuHann-Huei Tsai...
    638-642页
    查看更多>>摘要：This brief proposes a cryogenic stacked inverter-based gain-flattening low-noise amplifier (LNA) with dual current reuse and dual noise-canceling in 28-nm CMOS. The LNA features a current-reuse high-Q gate inductor and cascode inverter-based input stage with shunt-resistive feedback, optimizing wideband input impedance. A cryogenic aware self-body bias (SBB) mitigates $V_{\mathrm { th}}$ and $r_{\mathrm { out}}$ variations at cryogenic temperatures. The design incorporates a source-degenerated common-source (CS) main amplifier, followed by current reuse inductor gain peaking cascode dual noise-canceling CS transistors, enhancing transconductance and suppressing noise in both main and auxiliary amplifiers. At cryogenic temperature (4 K), the LNA achieves a measured peak gain $(S_{21})$ of 43.4 dB, with a large 3-dB bandwidth from 0.02 – 3.2 GHz (197.5% fractional BW) and a minimum NF of 0.37 dB (corresponding to noise temperature $T_{N}$ of 25.8 K) at 0.7 GHz under power dissipation of 7.6 mW. The circuit occupies an active area of 0.31 mm2.
      原文链接:
    • NETL
    • NSTL
    • IEEE

    A Nanopower Folded-Cascode EEG Lowpass Filter

    Surachoke ThanapitakKhanittha KaewdangXiao LiuPrajuab Pawarangkoon...
    643-647页
    查看更多>>摘要：This brief presents a continuous-time lowpass biquadratic cell developed from a folded-cascode OTA operating in the subthreshold region. The proposed cell has been implemented by configuring the OTA in a unity-gain feedback manner and inserting two individual capacitors into the output and internal folding nodes. This allows the proposed biquadratic cell to benefit from the high loop gain that maintains good linearity at passband frequencies well below its cutoff. As an application of this biquadratic cell, a pseudo-differential lowpass filter for electroencephalogram detection is designed and implemented in a 0.18- $\mu $ m standard CMOS technology. The custom filter occupies a silicon area of $230~\mu $ m $\times 300~\mu $ m and operates from a 0.8-V dc supply with 7 nA total current consumption. Multi-chip measurements exhibit the average cut-off frequency at 151.2 Hz, input-referred noise of $35~\mu $ Vrms, and linear range of 110 mVP. This brief achieves the best FoM to date among recent relevant nano-power filters.
      原文链接:
    • NETL
    • NSTL
    • IEEE

    A 1-Mbps 0.7-nJ/Bit Low-Complexity High-Robust FM-UWB Transmitter Under a Sub-1-V Supply

    Yifan LiBo ZhouYuyang DingYun Hao...
    648-652页
    查看更多>>摘要：A frequency-modulated ultra-wideband (FM-UWB) transmitter is fabricated in 65-nm CMOS, to feature high data rate, high energy efficiency, low complexity, and high robustness. A dual-modulus divider with duty-cycle correction and a square-to-triangular converter with a common-mode feedback unit, are for subcarrier generation. A dual-path ring current-controlled oscillator is for linear FM, and followed by a high-robust small-sized power amplifier. An all-digital automatic frequency control loop calibrates the carrier frequency. Experimental results show that the 3.75-4.25 GHz transmitter generates an FCC-compliant UWB signal, and has an energy efficiency of 0.7 nJ/bit under a data rate of 1 Mbps and a sub-1-V supply, with an active area of 0.14 mm2 and phase noise of –77 dBc/Hz at 1-MHz offset, as well as an output power of –14.3 dBm. Especially, both the subcarrier generator and the PA are different from the existing literature.
      原文链接:
    • NETL
    • NSTL
    • IEEE

    A 10 to 15 GHz Digital Step Attenuator With Robust Temperature Tolerance Across -55 ∘C to 125 ∘C

    Jiang LuoYao PengQiang Cheng
    653-657页
    查看更多>>摘要：This brief presents an efficient adaptive analog temperature compensation technique that stabilizes the amplitude and phase performance of an RF attenuator over an ultra-wide temperature range without compromising its other metrics. The approach utilizes an adaptive analog temperature-dependent voltage source (AATVS) to supply the binary digital control array, which indirectly biases the gate terminals of MOSFET switches in the attenuation unit. This method effectively mitigates thermal variations in on-resistance and intrinsic capacitance. To validate the technique, a 5-bit digital step attenuator (DSA) was designed and fabricated using a $0.13~\mu $ m SiGe BiCMOS process. The DSA exhibited excellent consistency in root-mean-square (RMS) amplitude and phase errors across $- 55~^{\circ }$ C to $125~^{\circ }$ C, achieving an RMS attenuation error below 0.24 dB, an RMS phase error under 2.3°, and an insertion loss (IL) better than 4.9 dB over 10–15 GHz. To the best of the authors’ knowledge, this letter is the first to implement an AATVS-based compensation mechanism in a 5-bit DSA, ensuring stable amplitude and phase accuracy under extreme thermal variations.
      原文链接:
    • NETL
    • NSTL
    • IEEE

    A V-Band FMCW Signal Generator With Hybrid Dual-Path VCO Technique Achieving 13.6-GHz Chirp Bandwidth

    Jiangbo ChenShengjie WangQuanyong LiWenyan Zhao...
    658-662页
    查看更多>>摘要：This brief presents a V-band frequency-modulation continuous wave (FMCW) signal generator for high-resolution radar applications. The proposed hybrid dual-path voltage-controlled oscillator (VCO) employs a digital-assisted capacitance decoding scheme, fully utilizing the tunable capacitance to achieve wideband chirping while maintaining high chirp linearity. To verify the proposed scheme, a radar transceiver with two transmit (TX) channels, and four receive (RX) channels is designed and fabricated in a 65-nm CMOS process. The FMCW signal generator occupies 2.98 mm2 and consumes 120 mW. A measured maximum chirp bandwidth of 13.6 GHz is achieved at TX output with an rms frequency error of 0.008%. The measured phase noise of the VCO is −97.37 dBc/Hz at a 1-MHz offset from a 60-GHz carrier. The proposed FMCW signal generator demonstrates a state-of-the-art chirp bandwidth at V-band.
      原文链接:
    • NETL
    • NSTL
    • IEEE

    Multi-Bit Capacitance Sensing System Using a-IGZO TFT Technology for Smart Wearables

    Bhawna TiwariSuyash ShrivastavaVaishali ChoudharyPydi Ganga Bahubalindruni...
    663-667页
    查看更多>>摘要：This brief presents a novel multi-bit Capacitance-to-Digital converter (CDC) using unipolar single-gate amorphous-Indium-Gallium-Zinc-Oxide thin-film transistors (a-IGZO TFTs). This circuit is fabricated on a $30{\mathrm {\,}} \mu $ m thick polyimide substrate with an active area of $6.5{\mathrm {\,}}$ mm2. The proposed CDC is designed by employing Charge-Sharing Successive-Approximation Register Analog-to-Digital Converter (CS SAR ADC). Further, the design facilitates integration of capacitance sensor/array directly with the ADC, hence the additional interfacing circuits between the capacitive-sensor and the ADC can be eliminated to make the system compact and energy-efficient. The functionality of the proposed CDC is demonstrated for a sensor capacitance value ranging from $1{\mathrm {\,}}$ pF to $31{\mathrm {\,}}$ pF. From measurements it is observed that the minimum value of capacitance that can be detected with the proposed CDC is around $2{\mathrm {\,}}$ pF, while the state-of-the-art CDC is around $3.7{\mathrm {\,}}$ pF, which is reported on a truly flexible substrate. Further, the ADC deployed in the CDC has resulted in an SNR of $35.57{\mathrm {\,}}$ dB, figure-of-merit (FoM) of $19.9{\mathrm {\,}}$ nJ/c.s., ENOB of $5.6{\mathrm {\,}}$ bits, differential non-linearity (DNL) of $0.52{\mathrm {\,}}$ LSB and an integral non-linearity (INL) of $0.81{\mathrm {\,}}$ LSB. At a sampling frequency of $2.08{\mathrm {\,}}$ kHz, the ADC has shown a total power dissipation of $2.02{\mathrm {\,}}$ mW with a supply voltage $(V_{DD})$ of $4{\mathrm {\,}}$ V. This capacitance sensing system finds potential applications in areas of biomedical, healthcare, and smart packaging systems etc, which need truly flexible devices.
      原文链接:
    • NETL
    • NSTL
    • IEEE

    High-Power 270-GHz Oscillator With Harmonic Output Power Optimization Using Series Resonance Feedback

    Abdul QahirKyung-Sik ChoiJong-Phil HongSang-Gug Lee...
    668-672页
    查看更多>>摘要：This brief proposes a high-power harmonic oscillator topology that adopts a series LC resonant feedback network to minimize the effective parasitic capacitance of the oscillator at the fundamental frequency while increasing the output power at the second harmonic by enabling a larger transistor size and minimizing the common-mode output conductance. Implemented in the 28-nm CMOS technology, the proposed 270-GHz oscillator achieves a peak output power of −3.2 dBm, a peak dc-to-RF efficiency of 0.81% and phase noise values of −56.8, −84.68 and −90.12 dBc/Hz at 100 kHz, 1 MHz and 10 MHz offsets, respectively.
      原文链接:
    • NETL
    • NSTL
    • IEEE