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中国邮电高校学报（英文版）
中国邮电高校学报（英文版）

郭更生

双月刊

1005-8885

jcupt@bupt.edu.cn

010-62282493

100876

北京邮电大学教一楼119室

中国邮电高校学报（英文版）/Journal The Journal of China Universities of Posts and TelecommunicationsCSCD北大核心EI
查看更多>>本刊是国内外公开发行的“以信息科学”为特色的学术性科技核心期刊。创刊于1994年，主要刊载通信与信息系统、信号与信息处理、计算机软件与理论、计算机应用技术、电磁场与微波技术、微电子学与固体电子学、控制理论与控制工程、管理科学与工程以及相关基础技术领域的学术论文、研究报告、综述、研究简报及学位论文等。
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    Predicting stability of integrated circuit test equipment using upper side boundary values of normal distribution

    Zhan WenfaHu XinyiZheng JiangyunYu Chuxian...
    85-93页
    查看更多>>摘要：In response to the growing complexity and performance of integrated circuit(IC),there is an urgent need to enhance the testing and stability of IC test equipment.A method was proposed to predict equipment stability using the upper side boundary value of normal distribution.Initially,the K-means clustering algorithm classifies and analyzes sample data.The accuracy of this boundary value is compared under two common confidence levels to select the optimal threshold.A range is then defined to categorize unqualified test data.Through experimental verification,the method achieves the purpose of measuring the stability of qualitative IC equipment through a deterministic threshold value and judging the stability of the equipment by comparing the number of unqualified data with the threshold value,which realizes the goal of long-term operation monitoring and stability analysis of IC test equipment.
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    Design and implementation of a multi-tile parallel scanning rasterization accelerator

    Xing LidongGuo QiangPeng XinlongFeng Zhenfu...
    94-104页
    查看更多>>摘要：In the design of a graphic processing unit(GPU),the processing speed of triangle rasterization is an important factor that determines the performance of the GPU.An architecture of a multi-tile parallel-scan rasterization accelerator was proposed in this paper.The accelerator uses a bounding box algorithm to improve scanning efficiency.It rasterizes multiple tiles in parallel and scans multiple lines at the same time within each tile.This highly parallel approach drastically improves the performance of rasterization.Using the 65 nm process standard cell library of Semiconductor Manufacturing International Corporation(SMIC),the accelerator can be synthesized to a maximum clock frequency of 220 MHz.An implementation on the Genesys2 field programmable gate array(FPGA)board fully verifies the functionality of the accelerator.The implementation shows a significant improvement in rendering speed and efficiency and proves its suitability for high-performance rasterization.
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    Convolutional neural network adaptation and optimization method in SIMT computing mode

    Feng ZhenfuZhang YayingYang LeleXing Lidong...
    105-112页
    查看更多>>摘要：For studying and optimizing the performance of general-purpose computing on graphics processing units(GPGPU)based on single instruction multiple threads(SIMT)processor about the neural network application,this work contributes a self-developed SIMT processor named Pomelo and correlated assembly program.The parallel mechanism of SIMT computing mode and self-developed Pomelo processor is briefly introduced.A common convolutional neural network(CNN)is built to verify the compatibility and functionality of the Pomelo processor.CNN computing flow with task level and hardware level optimization is adopted on the Pomelo processor.A specific algorithm for organizing a Z-shaped memory structure is developed,which addresses reducing memory access in mass data computing tasks.Performing the above-combined adaptation and optimization strategy,the experimental result demonstrates that reducing memory access in SIMT computing mode plays a crucial role in improving performance.A 6.52 times performance is achieved on the 4 processing elements case.
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