Aiming at the nonlinear problems caused by sampling capacitor mismatch and operational amplifier gain error in the Pipelined analog-to-digital converter(ADC),a calibration technique combi-ning foreground and background was proposed.The foreground calibration technique compensated the quantization results of the corresponding pipeline level by analyzing the residual of the ADC quantization results.The background calibration technique was based on pseudorandom(PN)injection and utilized the statistical characteristics of PN to calibrate gain errors.On the basis of system level modeling and RTL level circuit design,this calibration technique achieved field-programmable gate array(FPGA)verification and the chip was successful fabricated.The test results show that at a sampling rate of 1 GS/s,a Pipelined ADC with a calibration accuracy of 14 bit has an increase in effective number from 9.30 bit to 9.99 bit,about 4 dB increase in signal-to-noise ratio,9.5 dB increase in the range without dynamic spurious noise,and a decrease in integral nonlinearity(INL)of about 10 LSB.
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