Aiming at the problems of large computational complexity,time-consuming,and high resource requirements of convolutional neural network(CNN),this paper proposes a design scheme of binary neural network(BNN)image classification model running on embedded platforms with limited resources and power consumption in mobile terminals and designs a hardware acceleration design for its implementation on an ARM+FPGA platform.By converting the convolution multiply-accumulate operation into XNOR logic and popcount operations,the computational complexity and on-chip resource requirements are reduced.Data multiplexing,pipeline design,and parallel calculation were utilized to increase overall computation speed.Taking image recognition under the CIFAR-10 data set as an example,We use VIVADO HLS tool to complete the deployment of convolutional neural network model on FPGA platform.The test results on the PYNQ-Z2 platform show that the network model deployed on the FPGA side achieves a processing speed of approximately 631 FPS at a working frequency of 100 MHz,total runtime is only about 1.58 ms for image inputs of any size,after cropping on the processing system(PS)side.
维普
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