BIST supported design and realization of reed-solomon encoder and decoder on domestic FPGA
Reed-Solomon code is one kind of error correction codes which has been widely used,since some domestic FPGA platforms do not provide the use of this IP core and the requirements of using shared module in different FPGA platforms in project,low-complexity and low resource usage Reed-Solomon encoder and RS decoder are designed in this paper,and the method of FPGA resource optimization is proposed,co-simulated with Matlab and Modelsim is used to verify the correctness and rationality of designed RS encoder and RS decoder circuit,and it's implemented on EG4S20NG88 and PH1A100GCG324 of Anlu Technology which is domestic FPGA manufacturer and XC7K325TFFG900 of Xilinx which is foreign FPGA manufacturer.Meantime,the PRBS module is added to implement Built-in Self-Test function which greatly reduces the time of porting the module among different FPGA platforms.
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