首页|一种进行环路隔离的大电流高电源抑制比LDO设计

一种进行环路隔离的大电流高电源抑制比LDO设计

Design of a high current and high power supply rejection ratio LDO using loop isolation

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针对传统带有电荷泵、以 NMOS作为功率管的 LDO 驱动能力低下和输出纹波偏高的问题,基于 Huahong 0.35 μm BCD工艺,设计了一种隔离交直流环路的大电流 LDO.该 LDO 通过将直流环路和交流环路进行隔离,降低了对电荷泵驱动能力的需求,从而保证 NMOS功率管栅极驱动电压的较低纹波并实现大电流输出.通过加入纹波电流吸收电路,增强了 LDO 的PSRR.结果表明,在 3.41~5.5 V的输入电压范围内,LDO 的输出电压为 3.3 V,输出电流最高达到 3 A,压差为 110 mV.LDO 在轻负载下的 PSRR 为:111.261 dB@DC,86.900 5 dB@1 kHz,78.947 2 dB@1 MHz;重负载下的PSRR为:111.280 dB@DC,84.123 1 dB@1 kHz,39.263 8 dB@1 MHz.
In view of the problems of low driving capability and high output ripple in traditional LDO with charge pump and NMOS as power transistor,a high-current LDO with isolated AC-DC loops was designed based on Huahong 0.35 μm BCD process.The demand for charge pump driving capability in this LDO is reduced by isolating the DC loop and AC loop,thereby ensuring low ripple in the gate driving voltage of the NMOS power transistor and achieve high current output.The PSRR of LDO is enhanced by adding ripple current absorbing circuit.The results show that in the input voltage range of 3.41~5.5 V,the output voltage of LDO is 3.3 V and the output current can reach 3 A.The PSRR of LDO under light load is 111.261 dB@DC,86.900 5 dB@1 kHz,78.947 2 dB@1 MHz.The PSRR under heavy load is 111.280 dB@DC,84.123 1 dB@1 kHz,39.263 8 dB@1 MHz.

NMOS LDOhigh currentloop isolationhigh PSRR

张加宏、沙秩生、王泽林、刘祖韬、邹循成

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南京信息工程大学集成电路学院 南京 210044

南京信息工程大学江苏省大气环境与装备技术协同创新中心 南京 210044

NMOS LDO 大电流 环路隔离 高PSRR

国家重点研发计划国家重点研发计划

2022YFB32059022022YFB3205903

2024

电子测量技术
北京无线电技术研究所

电子测量技术

CSTPCD北大核心
影响因子:1.166
ISSN:1002-7300
年,卷(期):2024.47(3)
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