In view of the high-resolution requirements of single-photon counters for high-speed flight photon time measurement,the traditional time-to-digital converter TDC has the disadvantage of large errors in time measurement. This paper designs a TDC that uses the internal logic delay unit Carry4 of the FPGA to cascade to build a delay chain. The method firstly uses the method of sub chain average to sample the data and avoid the data "bubble". Secondly,the width of each delay cell is calibrated to nearly uniform width by combining the code density test and bin-by-bin calibration to improve the measurement accuracy of the system. Finally,Vivado software was simulated and burned to ZYNQ7000 for board-level testing. The experimental results show that the TDC can achieve time resolution 10.91 ps in the dynamic time range of 3 ns. DNL(DNL) range is[0.75,1.01]LSB,INL (INL) range for[1.74,2.19]LSB.
关键词
FPGA/时间数字转换/Carry4/码密度测试/差分非线性/积分非线性
Key words
FPGA/time digital conversion/Carry4/code density test/DNL/INL
维普
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