导航GNSS芯片作为导航产品发展的核心部件,伴随其工艺制程越来越先进,功耗问题已成为影响其发展的关键因素,同时传统UPF(unified power format)低功耗物理设计流程存在纠错成本高,验证困难等缺点.以TSMC 22 nm工艺下GNSS芯片的DMAREQ_2模块为例,提出一种V-UPF(Verfiery-UPF)流程,在物理设计前后应用VC LP对设计文件全面静态低功耗验证.设计中通过规划多电压域、插入多种特殊低功耗单元,同时对电源开关单元采用daisy chain连接和交叉布局来降低系统功耗,使用Blockage技术降低电压域之间电平信号转化带来的泄露功耗与峰值功耗.最后,通过Prime time-PX进行功耗分析.结果表明,在不同的工作环境下,总体功耗最多降低37.4％,静态功耗最多降低45.2％,动态功耗最多降低23.2％,本设计功耗优化效果显著.
Low-power physical design and verification of GNSS chip based on V-UPF
As the core component of the development of navigation products,the navigation GNSS chip has become more and more advanced with its process,and the power consumption problem has become a key factor affecting its development.At the same time,the traditional UPF(unified power format)low-power physical design process has shortcomings such as high error correction costs and difficult verification.This paper takes the DMAREQ_2 module of the GNSS chip under the TSMC 22 nm process as an exam-ple,and proposes V-UPF(Verfiery-UPF)process,which uses VC LP to verify the design files in a comprehensive static low power consumption before and after the physical design.In the design,multi-voltage domains are planned,a variety of special low-power units are inserted,and daisy chain connections and crossover layouts are used for power switch units to reduce system power con-sumption.Blockage technology is used to reduce the level signal conversion between voltage domains.Leakage and peak power dis-sipation.Finally,power consumption analysis is performed by Prime time-PX The results show that under different working envi-ronments,the total power consumption is reduced by up to 37.4％,the leakage power consumption is reduced by up to 45.2％,and the dynamic power consumption is reduced by up to 23.2％.The power consumption optimization effect of this design is remarkable.
万方数据
维普
