A digital calibration technique for sampling clock phase mismatch for TI-ADC
In order to solve the problem that the sampling clock offset mismatch has a great impact on the performance of multi-phase time interleaved sampling analog-to-digital converter(TI-ADC),a phase error extraction technique that cross-correlates the output of the sampling channel and uses the first-order Taylor expansion for adaptive compensation calibration is proposed,which effectively compensates for the multi-channel timing mismatch.Based on the 65 nm CMOS process,a 12 bit 1.6 GS/s eight-phase TI-ADC sampling phase mismatch calibration circuit was designed.When the input signal frequency is 626.562 5 MHz,the effective number of bits of the calibrated TI-ADC is increased by 6.29 bit,the signal-to-noise distortion ratio is increased by 38.1 dB,and the spurious-free dynamic range is increased by 44.44 dB.The design results show that the proposed technology has a simple structure and low hardware resource consumption,which can significantly improve the sampling performance of TI-ADC system.
TI-ADCphase offset mismatchmutual correlationfirst order Tayloradaptive calibration
万方数据
维普
