配备PoC(Power over Coax)电感网络的串行解串器(SerDes)高速链路在应用中,经常遇到插入损耗(S21)性能陡降的技术问题,通过对PoC电感网络进行分布参数的数值建模及计算推导分析,研究发现印制电路板(PCB)的寄生电容会引起PoC网络中高品质因数电感的强烈阻抗谐振,从而导致 S21 问题的产生,通过合理的PCB优化措施,可以将影响最小化,并通过仿真和测试,进一步验证了数值建模预判方法的合理性和准确性.
Numerical Modeling and Analysis Method Based on PoC Inductive Network
In applications of high-speed links with Serializers/Deserializers(SerDes)equipped with Power over Coax(PoC)inductive networks,the technical issue of steep performance degradation of inser-tion loss(S21)is often encountered.Through numerical modeling and computational analysis of the PoC inductive network,it is found that the parasitic capacitance of printed circuit board(PCB)can cause strong impedance resonance in high-quality factor inductors in the PoC network,leading to the occurrence of S21 problems.By implementing reasonable PCB optimization measures,the impact can be minimized.Simula-tion and testing further validate the rationality and accuracy of the numerical modeling predictive method.
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