Design and Implementation of Arbitrary Multiple Resampling FPGA Based on Farrow Architecture
Arbitrary waveform generators usually employ direct digital waveform synthesis techniques to generate arbitrary wave-form.However,when this technology is used to achieve a variable sampling rate,it needs to adjust the working frequency of the clock,resulting in image frequencies that are difficult to filter out in the output and increasing the complexity of hardware implementa-tion.To address these issues,research is conducted on an arbitrary multiple resampling method based on the Farrow architecture.A parallel implementation of a 32-channel arbitrary resampling system is designed and realized on an FPGA under a fixed clock drive.Additionally,a logical implementation scheme for clearing error accumulation is proposed to accumulate quantization errors in logical implementation.Experimental results demonstrate that the system achieves sampling rate conversion from 1 ksps to 6 Gsps with a fixed clock frequency of 187.5 MHz and effectively solves waveform distortion caused by quantization error accumulation during long-term operation.
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维普
