为降低电磁干扰对信号传输的影响,分析了应答器上行链路信号传输过程及其易遭受干扰信号的特点,设计了基于符号最小均方误差(least mean square,LMS)算法的自适应解调方法.为在硬件平台中实现该解调方法,通过仿真计算,确定LMS算法的自适应算法中间变量变化范围,使用截位操作完成权值系数的更新,设置均衡器长度、步长因子、中值滤波系数分别为1、1/64、16,可在不占用过多硬件资源情况下获得良好的解调性能.解调算法在现场可编程门阵列(field programmable gata array,FPGA)上予以验证,实验表明,当信噪比为6 dB时,FPGA中自适应解调误码率为0.000 001,在信噪比大于等于6 dB时,实测误码率与仿真分析误码率基本一致;FPGA自适应解调方法在列车不同速度等级下误码率均小于10-6.
Abstract
In order to reduce the impact of electromagnetic interference on signal transmission,the balise uplink signal transmission process and its susceptibility to interference signals were analyzed,and an adaptive demodulation method based on the symbolic least mean square(LMS)algorithm was designed.In order to achieve the demodulation method in the hardware platform,the range of the in-termediate variable of the adaptive algorithm of LMS algorithm was determined through simulation calculation.And the weight coeffi-cient was updated by truncation operation.Setting the equalizer length,step factor,and median filter coefficient to 1,1/64,and 16,respectively,can obtain excellent demodulation performance without occupying too much hardware resources.The demodulation algo-rithm was verified on field programmable gata array(FPGA).The experiment shows that the bit error rate of adaptive demodulation in FPGA is 0.000 001 when the signal-to-noise ratio is 6 dB.And the measured bit error rate is basically consistent with the simulation bit error rate when the signal-to-noise ratio is greater than or equal to 6 dB.The bit error rate of FPGA adaptive demodulation method is less than 10-6 at different train speed levels.
关键词
应答器/自适应解调/最小均方误差(LMS)算法/现场可编程门阵列(FPGA)/信噪比/误码率
Key words
balise/adaptive demodulation/least mean square(LMS)algorithm/field programmable gata array(FPGA)/signal-to-noise ratio/bit error rate
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