随着后端互连间距和横截面积的持续减小,Cu面临着电阻率、电迁移和RC延迟等挑战.石墨烯覆盖Cu后形成的复合材料(Cu-Gr),可以显著降低Cu线电阻率,提高其电流密度与抗电迁移性能,能有效应对当前纯Cu互连所面临的挑战.本文首先采用物理气相沉积(physical vapor deposition,PVD)制备了 100 nm厚的Cu膜,并通过Ar+射频清洗改善了其表面能.然后利用等离子体化学气相沉积(plasma enhanced chemical vapor deposition,PECVD)在Cu表面沉积石墨烯,通过调节衬底偏压至75V,最终在Cu表面沉积出了具有低缺陷密度、较高平整度的少层石墨烯结构的碳薄膜.随后,对Cu-Gr进行了 350℃热退火处理来改善其导电性能.结果表明,热退火处理前,在75 V衬底偏压下Cu-Gr的电导率最高,相比较热退火前的Cu,其电导率提升12.64％.热退火处理后,在50 V衬底偏压下Cu-Gr的电导率最高,相比较热退火后的Cu,其电导率提升12.75％.此外,ANSYS有限元分析表明将Cu-Gr应用于超大规模集成电路(very large scale integration circuit,VLSI)互连结构中,在通孔附近的等效热应力最高,其值为35.8 MPa.上层Cu-Gr互连位置等效弹性应变最大,其值为1.1×10-4.
Preparation of new Cu-Gr composite materials for future interconnects by PECVD
The reduction in the size of interconnects at the rear end presents Cu with obstacles like resistivity,electromigration,and RC delay.The combination of Cu and graphene,known as Cu-Gr,offers a solution.It lowers the resistivity of Cu wires,enhances their current density,and provides better resistance to migration.This innovation effectively tackles the existing issues with pure Cu interconnects.Additionally,the plasma enhanced chemical vaper deposition(PECVD)technique offers a practical method for producing graphene at lower temperatures,in line with the current manufacturing process for silicon-based integrated circuits.The Cu-Gr composites were fabricated as follows.Initially,100 nm thick Cu was deposited on the Si/SiO2 substrate using physical vapor deposition(PVD)technology.Subsequently,graphene was applied to the Cu surface using a PECVD process.Before deposition,the sample was heated to 600℃ in a low-pressure environment.This was succeeded by radio frequency cleaning,where Ar was utilized to enhance the flatness and wettability of the Cu surface.Afterward,hydrogen and methane were introduced as process gases to deposit graphene under different substrate bias pressures.Upon completion of the growth,the samples were cooled down to 200℃ in Ar and returned to the injection chamber.This paper mainly studied the impact of substrate bias on graphene deposited on Cu via the PECVD process.It also investigated the electrical conductivity of Cu-Gr before and after heat treatment at 350℃,as well as its thermal stress in very large scale integration circuit(VLSI)interconnections using ANSYS.The principal discussions and conclusions are presented below.(1)Raman spectroscopy analysis confirmed the successful synthesis of graphene structures on Cu substrates under both 75 and 100 V substrate biases.Notably,when biased at 75 V,the graphene structures exhibited a reduced number of layers and a lower defect density,indicative of improved quality.Atomic force microscope(AFM)study further showed that the surface roughness of the samples prepared at 75 V bias was low and the morphology was relatively smooth.Additionally,scanning electron microscope(SEM)examinations revealed that the average sizes of carbon particles on the sample surfaces prepared at 75 and 100 V biases were comparable,with measurements of 50.46 and 49.63 nm,respectively.This phenomenon can be rationalized by the diminished activity of the Cu substrate at lower temperatures,which constrains the diffusion kinetics of carbon atoms,thus leading to comparable particle sizes under both bias conditions.(2)The Cu-Gr was thermally annealed at 350℃.The results showed that the conductivity of Cu-Gr was the highest when the substrate was biased at 75 V,which was 6.17×107 S/m.Compared with the conductivity of Cu before annealing,the conductivity of Cu was increased by 12.64％.After heat treatment,the conductivity of Cu-Gr was further improved due to the increase of the grain size on the surface of Cu and the improvement of carbon film structures on the surface of Cu,and reached the maximum value of6.62×107 S/m when the substrate bias was 50 V.Compared with the electrical conductivity of Cu after annealing,the electrical conductivity of Cu was increased by 12.75％.(3)The Cu-Gr composites in VLSI interconnects generated the maximum thermal stress near the through-hole,with a value of 35.8 MPa.The maximum elastic strain occurred at the interface of the upper layer of Cu in contact with graphene with a value of 1.1×10-4.Therefore,further improvement of the interfacial contact between Cu and graphene and optimization of the structural design of complex wiring locations are required to improve the thermal stability of the interconnect structure.
new interconnect materialsgrapheneplasma enhanced chemical vapor depositionsubstrate biaselectrical conductivitythermal stress
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