In the preprocessing of large bandwidth digital intermediate frequency(IF)signals in the airborne radar or electronic warfare receiving system,the traditional parallel polyphase filtering has the drawback of consuming exces-sive FPGA's multiplier resource.A method with construction of fast filtering algorithm by parallel polyphase decomposi-tion coefficients is proposed to realize digital down conversion(DDC)processing of high-speed ADC sampling rate between 4 GS/s and 8 GS/s.First,the IF sampling signal is decomposed into 32 parallel branches.Then,the parallelism of the baseband complex signal is reduced to 16 through digital mixing and double decimation.Finally,to realize DDC processing of high sampling rate and large bandwidth signal,the 16-phase fast filtering architecture based on the short convolution algorithm is constructed.Through the design and application of wideband DDC based on 16-phase fast filtering,the FPGA multiplier resource is reduced to about 32%of the traditional parallel polyphase filtering,which greatly saves FPGA's resource and improves the preprocessing ability of single FPGA for multi-channel and large bandwidth signals.
sampling rate16-phase fast filterdigital down conversionFPGA
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