Design of an Improved Shared Boolean Logic Carry Select Adder
In today's highly digitized and computationally intensive environment,it is crucial to design high-speed and low-power adders,such as Carry Select Adders(CSLA).Based on this,an improved shared Boolean logic Carry Select Adder is proposed.Compared to existing designs,this design reduces the number of transistors on the basis of sacrificing some power consumption and speed.This design utilizes TSMC65 nm technology to achieve 4-bit design in Cadence.The simulation results show that compared to the Fast Adder Module-2(FAM2)Carry Select Adder,this scheme reduces the number of transistors,power consumption,and power consumption delay product by 8.91％,8.13％,and 6.02％,respectively.
Carry Select Adderthe number of transistorspower consumptiondelay
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