Triple-node Upset Tolerant Latch Design Based on Input-separated C-element in 32 nm Process
As the feature size of integrated circuits continues to decrease,the probability of multi-node upset due to single particle effect in storage circuits is increasing,which seriously affects the reliability of the circuits.Therefore,to increase the radiation hardening capability and reliability of the circuit,a triple-node upset hardened latch,TNUTL,is proposed.The latch uses dual-mode redundancy and input separated C-element to achieve 100%triple-node upset tolerance.The use of clocking techniques and transmission gates effectively reduces the power consumption and delay of the latch.The simulation results under 32 nm CMOS process show that the proposed latch reduces power consumption by 36.84%and delay by 65.31%on average as well as power-delay product by 82.13%as compared to the same type of structure.
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