一种超低损耗理想二极管设计
Design of an Ultra-low Loss Ideal Diode
陈石平 1李烁瀚 1凡飞飞 1陈金杰 2冯俊劼1
作者信息
- 1. 广东科贸职业学院,广东 广州 511500
- 2. 湖南城市学院,湖南 益阳 413000
- 折叠
摘要
首先文章介绍了目前实现理想二极管技术方案优缺点,对方案进行改进,设计一种超低损耗理想二极管控制电路,电路由PMOS主管、PMOS辅管、两个偏置电阻组成.优先选用相同参数、封装在一起的集成PMOS辅管和两个偏置电阻组成比较电路,控制PMOS主管的导通与截止,当输入电压VCC不小于输出电压Vout时,PMOS主管导通;反之PMOS主管截止,防止Vout电流倒灌至VCC,保护VCC电源前级电路.本设计的优势在于电路具有防止倒灌功能,可以保护前级电路;整个电路具有非常低静态电流损耗;组合逻辑比较电路简单,成本较低,实用性强.
Abstract
Firstly, this paper introduces the advantages and disadvantages of current technology scheme for realizing ideal diode, and it improves the scheme to design an ultra-low loss ideal diode control circuit, which consists of a PMOS main transistor, a PMOS auxiliary transistor, and two bias resistors. It is preferable to use an integrated PMOS auxiliary transistor with the same parameters and packaged together along with two bias resistors to form a comparison circuit, which controls the conduction and cutoff of the PMOS main transistor. When the input voltage VCC is not less than the output voltage Vout, the PMOS main transistor conducts. On the contrary, the PMOS supervisor cuts off to prevent Vout current from flowing back into the VCC and protect the front-end circuit of the VCC power supply. The advantage of this design is that the circuit has the function of preventing backflow, which can protect the front-end circuit. The entire circuit has very low static current loss. The combination logic comparison circuit is simple, low-cost, and highly practical.
关键词
超低损耗/理想二极管/PMOS辅管/倒灌电流Key words
ultra-low loss/ideal diode/PMOS auxiliary transistor/reverse current引用本文复制引用
出版年
2024
国家科技期刊平台
NSTL
万方数据