Solid-state non-volatile memories based on vdW heterostructure-based vertical-transport ferroelectric field-effect transistors

Qiyu YANG ¹Zheng-Dong LUO ¹Fei XIAO ²Junpeng ZHANG ³Dawei ZHANG ⁴Dongxin TAN ⁵Xuetao GAN ⁶Yan LIU ¹Zhufei CHU ⁷Yinshui XIA ⁷Genquan HAN¹

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作者信息

1. Hangzhou Institute of Technology,Xidian University,Hangzhou 311200,China;State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology,School of Microelectronics,Xidian University,Xi'an 710071,China
2. Hangzhou Institute of Technology,Xidian University,Hangzhou 311200,China
3. School of Artificial Intelligence,Xidian University,Xi'an 710071,China
4. School of Materials Science and Engineering,University of New South Wales(UNSW)Sydney,Sydney NSW 2052,Australia;ARC Centre of Excellence in Future Low-Energy Electronics Technologies(FLEET),University of New South Wales(UNSW)Sydney,Sydney NSW 2052,Australia
5. State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology,School of Microelectronics,Xidian University,Xi'an 710071,China
6. Key Laboratory of Light Field Manipulation and Information Acquisition,Ministry of Industry and Information Technology,and Shaanxi Key Laboratory of Optical Information Technology,School of Physical Science and Technology,Northwestern Polytechnical University,Xi'an 710129,China
7. Faculty of Electrical Engineering and Computer Science,Ningbo University,Ningbo 315211,China
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Abstract

Driven by the explosive development of data-centric computation applications,it is becoming urgent to develop in-memory computing devices that are beyond the von Neumann architecture with an ar-rangement of separated logic and memory components.The transistor-type solid-state non-volatile memories,such as ferroelectric field-effect transistors(FeFETs),have long been regarded as a competitive candidate for future in-memory computing architectures.However,the density scaling towards high-density arrays would require advanced FeFETs with reduced footprints,which remains a great challenge so far.Here,a vertical-transport(VT)FeFET that flips the charge transport channel perpendicular to the substrate plane is proposed,in which a ferroelectric gate and a van der Waals(vdW)heterojunction channel are vertically integrated,effectively reducing the device footprints.The proposed VT-FeFET shows not only the robust bi-nary non-volatile memory states but also several key synaptic functionalities at the device level.An artificial neural network with supervised learning was simulated based on the device conductance switching properties,showing excellent classification accuracy for the MNIST handwritten digits.These findings suggest that the proposed VT-FeFET could offer a new solution for future non-volatile memories as well as more advanced neuromorphic systems.

Key words

vdW heterostructure/non-volatile memory/vertical-transport transistor/ferroelectric field-effect transistor/memristive devices

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基金项目

National Key R&D Program of China(2023YFB4402303)

National Natural Science Foundation of China(62090033)

National Natural Science Foundation of China(62025402)

National Natural Science Foundation of China(62274128)

National Natural Science Foundation of China(92264202)

National Natural Science Foundation of China(62293522)

National Natural Science Foundation of China(92364204)

Zhejiang Provincial Natural Science Foundation of China(LDT23F04023F04)

Zhejiang Provincial Natural Science Foundation of China(LDT23F04024F04)

Zhejiang Provincial Natural Science Foundation of China(LR21F010003)

Fundamental Research Funds for the Central Universities(QTZX23079)

Key Research and Development Program of Ningbo City(2023Z071)

出版年

2024

中国科学:信息科学(英文版)

中国科学院

中国科学:信息科学(英文版)

CSTPCDEI

影响因子：0.715

ISSN：1674-733X

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