基于改进DDS的应答器动态检测系统2FSK调制器设计
Design of 2FSK Modulator for Balise Dynamic Detection System Based on Improved DPS
朱明勋 1吕旌阳 2许庆阳3
作者信息
- 1. 中国铁道科学研究院集团有限公司北京铁科英迈技术有限公司,北京 100081
- 2. 北京邮电大学信息与通信工程学院,北京 100876
- 3. 中国铁道科学研究院集团有限公司基础设施检测研究所,北京 100081
- 折叠
摘要
基于高速综合检测列车平台的应答器动态检测系统可实现对应答器相关设备性能的实时检测.为测试车载应答器动态检测系统的性能,需产生高精度可控波特率和载频的调制信号(2FSK)作为上行链路信号.基于直接数字频率合成器(DDS)技术,通过对相位累加模块和相幅转换模块进行设计,提出分段相位累加算法,计算同周期内相位增量和码元跳变处的相位增量;通过改进的坐标旋转数字计算方法(CORDIC)实时计算对应的信号幅值,用数字模拟转换器(DAC)将离散信号转换为模拟信号,从而实现频偏和数据速率可变且相位连续的信号调制.在相幅转换模块设计中,采用改进CORDIC算法替代传统的查表法,将相位增量转换成信号幅度,有效减少了现场可编程逻辑门阵列(FPGA)存储资源的开销.基于改进DDS的2FSK调制器设计方法,可为应答器动态检测系统提供高精度可控波特率和载频的2FSK调制信号,保证了应答器动态检测系统校准的准确性.
Abstract
The balise dynamic detection system based on the high speed comprehensive inspection train platform can implement real-time performance inspection of balise related equipment.To test the performance of the onboard balise dynamic detection system,it is necessary to generate high-precision modulated signals(2FSK)with controllable baud rates and carrier frequencies and use them as uplink signals.Based on direct digital synthesizer(DDS)technology,a segmented phase accumulation algorithm was developed by designing a phase accumulation module and a phase-amplitude conversion module.Additionally,the phase increment within the same period and that at the symbol jump were calculated.Furthermore,the signal amplitude was calculated in real time with an improved coordinate rotation digital computer(CORDIC)algorithm,and the discrete signals were converted into analog signals using a digital-to-analog converter(DAC)to modulate signals with variable frequency offset and data rate and continuous phase.In the design of the phase-to-amplitude conversion module,an improved CORDIC algorithm was used instead of the traditional look-up table method to convert phase increment to signal amplitude.This process effectively reduced the storage resource overhead of field programmable gate array(FPGA).The design of 2FSK modulator based on improved DDS can provide high-precision 2FSK modulated signals with controllable baud rates and carrier frequencies for the balise dynamic detection system,ensuring its calibration accuracy.
关键词
应答器动态检测系统/2FSK/DDS/分段相位累加/CORDIC/FPGAKey words
balise dynamic detection system/2FSK/DDS/segmented phase accumulation/CORDIC/FPGA引用本文复制引用
基金项目
中国铁道科学研究院集团有限公司科研开发基金(2020YJ219)
出版年
2024
NETL
NSTL
万方数据