首页|3D IC系统架构概述

3D IC系统架构概述

扫码查看
随着芯片制造工艺接近物理极限,使用多Die堆叠的三维集成电路(3D IC)已经成为延续摩尔定律的最佳途径之一.利用3D IC将芯片垂直堆叠集成,可以极大程度降低互联长度,提升互联带宽.详细介绍了一些常见的3D IC系统架构方案,说明了使用不同3D架构对于整体芯片系统在性能、功耗等方面的优势,也列举了在物理实现、封装测试、工艺能力等方面的挑战.最后综述了一些业内使用3D IC的典型产品,并介绍了这些产品的系统架构、典型参数、适用领域,以及使用3D IC后给产品带来的竞争力提升情况.针对业界现状,认为应该把握机遇,不惧挑战,实现弯道超车.
An Overview of 3D IC System Architecture
As the chip manufacturing process approaches its physical limits,multi-die stacking 3D integrated circuit(IC)technology has emerged as a promising approach to sustain Moore's law.Integrating chips vertically with 3D IC can significantly reduce interconnection length and improve interconnection bandwidth.This paper provides a detailed overview of common 3D IC system architecture solutions and discusses the advantages of using different 3D architectures in terms of performance,power,and area.It also outlines the challenges re-lated to physical implementation,packaging,testing,and process capability.This paper summarizes some typical commercial products that utilize 3D IC technology and introduces their system architecture,typical parameters,applicable fields,and competitiveness improvement.Considering the current industry landscape,the paper suggests that China should comprehensively assess the current situation,capitalize on opportunities,confront challenges without fear,and strive for leadership in this domain.

3D IC3D stack integrated circuit3D system on chipmemory on logiclogic on logic

陈昊、谢业磊、庞健、欧阳可青

展开 >

移动网络和移动多媒体技术国家重点实验室,中国 深圳 518055

深圳市中兴微电子技术有限公司,中国 深圳 518081

射频异质异构集成全国重点实验室,中国 深圳 518061

三维集成电路 三维堆叠芯片 三维片上系统 存储堆叠逻辑 逻辑堆叠逻辑

2024

中兴通讯技术
中兴通讯股份有限公司,安徽科学技术情报研究所

中兴通讯技术

CSTPCD北大核心
影响因子:1.272
ISSN:1009-6868
年,卷(期):2024.30(z1)