首页|High-performance and single event double-upset-immune latch design

High-performance and single event double-upset-immune latch design

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  • NETL
  • NSTL
  • Inst Engineering Technology-Iet
This Letter proposes a single event double-upset (SEDU)-fully-tolerant latch, referred to as FBSET, mainly featuring four interlocked branch circuits implemented by stacking three PMOS and one NMOS transistors or three NMOS and one PMOS transistors to achieve low power dissipation. The latch exhibits up to 84.56% area-power-delay product saving compared with recently reported latches. Simulation results validate that the proposed latch is completely immune to SEDU.

Zhang, Haineng、Liu, Zhongyang、Jiang, Jianwei、Xiao, Jun、Zhang, Zhengxuan、Zou, Shichang

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Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China|Shanghai Huahong Grace Semicond Mfg Corp, Shanghai 201203, Peoples R China|Univ Chinese Acad Sci, Beijing 100049, Peoples R China

Shanghai Huahong Grace Semicond Mfg Corp, Shanghai 201203, Peoples R China

Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Funct Mat Informat, Shanghai 200050, Peoples R China

2020

10.1049/el.2020.1823

Electronics letters

Electronics letters

SCI
ISSN：0013-5194
年,卷(期)：2020.56(23)
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